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ADM1021A
Table 4. ELECTRICAL CHARACTERISTICS (continued)
(T A = T MIN to T MAX , V DD = 3.0 V to 3.6 V, unless otherwise noted) (Note 1)
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
SMBus Interface (See Figure 2)
Logic Input High Voltage, V IH
STBY, SCLK, SDATA
Logic Input Low Voltage, V IL
STBY, SCLK, SDATA
SMBus Output Low Sink Current
ALERT Output Low Sink Current
Logic Input Current, I IH , I IL
SMBus Input Capacitance, SCLK, SDATA
SMBus Clock Frequency
SMBus Clock Low Time, t LOW
SMBus Clock High Time, t HIGH
SMBus Start Condition Setup Time,
t SU:STA
SMBus Repeat Start Condition
Setup Time, t SU:STA
SMBus Start Condition Hold Time, t HD:STA
SMBus Stop Condition Setup Time, t SU:STO
SMBus Data Valid to SCLK
Rising Edge Time, t SU:DAT
SMBus Data Hold Time, t BUF:DAT
SMBus Bus Free Time, t BUF
SCLK Falling Edge to SDATA
Valid Time, t VD:DAT
V DD = 3.0 V to 5.5 V
V DD = 3.0 V to 5.5 V
SDATA Forced to 0.6 V
ALERT Forced to 0.4 V
t LOW between 10% Points
t HIGH between 90% Points
Between 90% and 90% Points
Time from 10% of SDATA to 90% of SCLK
Time from 90% of SCLK to 10% of SDATA
Time for 10% or 90% of SDATA to 10% of SCLK
Time for 10% or 90% of SDATA to 10% of SCLK
Between Start/Stop Condition
Master Clocking in Data
2.2
?
6.0
1.0
? 1.0
?
?
4.7
4.0
4.7
250
250
4.0
4.0
250
250
0
4.7
?
?
?
?
?
?
?
5.0
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0.8
?
?
+1.0
?
100
?
?
?
?
?
?
?
?
?
?
?
1
1
V
V
mA
mA
m A
pF
kHz
m s
m s
m s
ns
ns
m s
m s
ns
ns
m s
m s
m s
m s
1. T MAX = 100 ? C, T MIN = 0 ? C
2. Operation at V DD = 5.0 V guaranteed by design; not production tested.
3. Guaranteed by design; not production tested.
t LOW
t R
t F
t HD; STA
SCLK
t HD; STA
t HD; DAT
t HIGH
t SU; DAT
t SU; STA
t SU; STO
SDATA
t BUF
STOP START
START
Figure 2. Serial Bus Timing
http://onsemi.com
4
STOP
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